867 search results - page 77 / 174 » The Design and Performance of a Conflict-Avoiding Cache |
120
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ISCA
2003
IEEE
15 years 5 months ago
2003
IEEE
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
103
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INFOCOM
2010
IEEE
14 years 10 months ago
2010
IEEE
—The delivery of video content is expected to gain huge momentum, fueled by the popularity of user-generated clips, growth of VoD libraries, and wide-spread deployment of IPTV se...
AINA
2007
IEEE
15 years 6 months ago
2007
IEEE
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
VLDB
2001
ACM
15 years 4 months ago
2001
ACM
Recent research addressed the importance of optimizing L2 cache utilization in the design of main memory indexes and proposed the so-called cache-conscious indexes such as the CSB...