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ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
14 years 9 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
DAC
2009
ACM
16 years 26 days ago
Online cache state dumping for processor debug
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
15 years 6 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
ASPLOS
1992
ACM
15 years 4 months ago
Application-Controlled Physical Memory using External Page-Cache Management
Next generation computer systems will have gigabytes of physical memory and processors in the 200 MIPS range or higher. While this trend suggests that memory management for most p...
Kieran Harty, David R. Cheriton
DSN
2006
IEEE
15 years 6 months ago
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...
Albert Meixner, Daniel J. Sorin