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» The Design and Performance of a Conflict-Avoiding Cache
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VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 7 days ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
91
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WWW
2005
ACM
16 years 16 days ago
Hierarchical substring caching for efficient content distribution to low-bandwidth clients
While overall bandwidth in the internet has grown rapidly over the last few years, and an increasing number of clients enjoy broadband connectivity, many others still access the i...
Utku Irmak, Torsten Suel
ICDE
2009
IEEE
150views Database» more  ICDE 2009»
16 years 1 months ago
Oracle Streams: A High Performance Implementation for Near Real Time Asynchronous Replication
We present the architectural design and recent performance optimizations of a state of the art commercial database replication technology provided in Oracle Streams. The underlying...
Lik Wong, Nimar S. Arora, Lei Gao, Thuvan Hoang, J...
IPPS
2009
IEEE
15 years 6 months ago
Scalable RDMA performance in PGAS languages
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
Montse Farreras, George Almási, Calin Casca...
HPCA
2005
IEEE
15 years 5 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...