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PARELEC
2006
IEEE
15 years 5 months ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich
IPPS
1999
IEEE
15 years 3 months ago
FPGA Implementation of Modular Exponentiation
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
Alexander Tiountchik, Elena Trichina
FCS
2006
15 years 13 days ago
Algorithmic Control in Concurrent Computations
: In this paper, functioning and interaction of distributed devices and concurrent algorithms are analyzed in the context of the theory of algorithms. Although different systems in...
Mark Burgin
CLUSTER
2009
IEEE
15 years 5 months ago
Combining I/O operations for multiple array variables in parallel netCDF
—Parallel netCDF (PnetCDF) is a popular library used in many scientific applications to store scientific datasets. It provides high-performance parallel I/O while maintaining ...
Kui Gao, Wei-keng Liao, Alok N. Choudhary, Robert ...
BMCBI
2007
97views more  BMCBI 2007»
14 years 11 months ago
A verification protocol for the probe sequences of Affymetrix genome arrays reveals high probe accuracy for studies in mouse, hu
Background: The Affymetrix GeneChip technology uses multiple probes per gene to measure its expression level. Individual probe signals can vary widely, which hampers proper interp...
Rudi Alberts, Peter Terpstra, Menno Hardonk, Leoni...