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CIBB
2009
15 years 29 days ago
On the Use of Temporal Formal Logic to Model Gene Regulatory Networks
Modelling activities in molecular biology face the difficulty of prediction to link molecular knowledge with cell phenotypes. Even when the interaction graph between molecules is k...
Gilles Bernot, Jean-Paul Comet
PATMOS
2005
Springer
15 years 5 months ago
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
TVLSI
2008
111views more  TVLSI 2008»
14 years 11 months ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
15 years 6 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...
JAIR
2010
160views more  JAIR 2010»
14 years 10 months ago
Reasoning About the Transfer of Control
We present DCL-PC: a logic for reasoning about how the abilities of agents and coalitions of agents are altered by transferring control from one agent to another. The logical foun...
Wiebe van der Hoek, Dirk Walther, Michael Wooldrid...