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AHS
2007
IEEE
222views Hardware» more  AHS 2007»
15 years 4 months ago
Programmable Analog VLSI Architecture Based upon Event Coding
Abstract— A programmable analog array inspired from neuronal spike event coding is presented. A configurable event block forms the basic building block of the programmable array...
Thomas Jacob Koickal, Alister Hamilton, Luiz C. P....
140
Voted
CLUSTER
2005
IEEE
15 years 10 months ago
Load Balancing using Grid-based Peer-to-Peer Parallel I/O
In the area of Grid computing, there is a growing need to process large amounts of data. To support this trend, we need to develop efficient parallel storage systems that can prov...
Yijian Wang, David R. Kaeli
MAM
2007
113views more  MAM 2007»
15 years 4 months ago
A reconfigurable computing framework for multi-scale cellular image processing
Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. Thes...
Reid B. Porter, Jan R. Frigo, Al Conti, Neal R. Ha...
136
Voted
IPPS
1999
IEEE
15 years 9 months ago
Infrastructure for Building Parallel Database Systems for Multi-Dimensional Data
Our study of a large set of scientific applications over the past three years indicates that the processing for multidimensional datasets is often highly stylized. The basic proce...
Chialin Chang, Renato Ferreira, Alan Sussman, Joel...
125
Voted
APCSAC
2000
IEEE
15 years 9 months ago
Cost/Performance Tradeoff of n-Select Square Root Implementations
Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fullypipelined n-select impl...
Wanming Chu, Yamin Li