2155 search results - page 119 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
151
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PPOPP
2010
ACM
16 years 2 months ago
2010
ACM
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
125
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ICPP
1997
IEEE
15 years 9 months ago
1997
IEEE
Communication characterization of parallel applications is essential to understand the interplay between architectures and applications in determining the maximum achievable perfo...
143
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COMPUTER
2002
15 years 4 months ago
2002
tail defines the level of abstraction used to implement the model's components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or n...
136
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HIPC
1999
Springer
15 years 9 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
148
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IPPS
2010
IEEE
15 years 2 months ago
2010
IEEE
Dynamic memory management is one of the most expensive but ubiquitous operations in many C/C++ applications. Additional features such as security checks, while desirable, further w...