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IPPS
2010
IEEE
15 years 2 months ago
Acceleration of spiking neural networks in emerging multi-core and GPU architectures
Recently, there has been strong interest in large-scale simulations of biological spiking neural networks (SNN) to model the human brain mechanisms and capture its inference capabi...
Mohammad A. Bhuiyan, Vivek K. Pallipuram, Melissa ...
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
15 years 11 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
IEEEPACT
2002
IEEE
15 years 10 months ago
Effective Compilation Support for Variable Instruction Set Architecture
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
Jack Liu, Timothy Kong, Fred C. Chow
143
Voted
IPPS
2006
IEEE
15 years 11 months ago
Dynamically reconfigurable cache architecture using adaptive block allocation policy
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
Milene Barbosa Carvalho, Luís Fabríc...
141
Voted
CCGRID
2006
IEEE
15 years 11 months ago
Exploit Failure Prediction for Adaptive Fault-Tolerance in Cluster Computing
As the scale of cluster computing grows, it is becoming hard for long-running applications to complete without facing failures on large-scale clusters. To address this issue, chec...
Yawei Li, Zhiling Lan