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ISCAS
2007
IEEE
202views Hardware» more  ISCAS 2007»
15 years 8 months ago
A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform
In this paper, an efficient VLSI architecture for a fast computation of the 2-D discrete wavelet transform (DWT) is proposed. The architecture employing a three-stage cascade in p...
Chengjun Zhang, Chunyan Wang, M. Omair Ahmad
SC
2000
ACM
15 years 6 months ago
Performance of Hybrid Message-Passing and Shared-Memory Parallelism for Discrete Element Modeling
The current trend in HPC hardware is towards clusters of shared-memory (SMP) compute nodes. For applications developers the major question is how best to program these SMP cluster...
D. S. Henty
ICPP
1999
IEEE
15 years 6 months ago
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures
Loops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the...
David López, Josep Llosa, Eduard Ayguad&eac...
IPPS
2010
IEEE
14 years 12 months ago
Performance improvements of real-time crowd simulations
The current challenge for crowd simulations is the design and development of a scalable system that is capable of simulating the individual behavior of millions of complex agents ...
Guillermo Vigueras, Juan M. Orduña, Miguel ...
IPPS
2002
IEEE
15 years 6 months ago
Real-Time Communication for Distributed Vision Processing Based on Imprecise Computation Model
In this paper we propose an efficient real-time communication mechanism for distributed vision processing. One of the biggest problems of distributed vision processing, as is the ...
Hiromasa Yoshimoto, Daisaku Arita, Rin-ichiro Tani...