2155 search results - page 302 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
149
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ECCV
2010
Springer
15 years 11 months ago
2010
Springer
This paper introduces an approach for dense 3D reconstruction from unregistered Internet-scale photo collections with about 3 million of images within the span of a day on a single...
177
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HPCA
2007
IEEE
16 years 6 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
156
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IPPS
2008
IEEE
16 years 14 days ago
2008
IEEE
This paper describes our early experiences with a preproduction Cray XMT system that implements a scalable shared memory architecture with hardware support for multithreading. Unl...
168
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ICPPW
2006
IEEE
16 years 3 days ago
2006
IEEE
Modulo scheduling is a major optimization of high performance compilers wherein The body of a loop is replaced by an overlapping of instructions from different iterations. Hence ...
156
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...