2155 search results - page 319 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
135
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HPCA
2007
IEEE
16 years 5 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
166
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IPPS
2006
IEEE
15 years 11 months ago
2006
IEEE
— This paper presents work-in-progress towards a C++ source-to-source translator that automatically seeks parallelisable code fragments and replaces them with code for a graphics...
137
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IPPS
1999
IEEE
15 years 9 months ago
1999
IEEE
PM-PVM is a portable implementation of PVM designed to work on SMP architectures supporting multithreading. PM-PVM portability is achieved through the implementation of the PVM fu...
140
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HPCA
1998
IEEE
15 years 9 months ago
1998
IEEE
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
152
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EUROPAR
2009
Springer
15 years 9 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...