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IEEEPACT
2002
IEEE
15 years 6 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
ARITH
2007
IEEE
15 years 8 months ago
A New Family of High.Performance Parallel Decimal Multipliers
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
Álvaro Vázquez, Elisardo Antelo, Pao...
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SC
2005
ACM
15 years 7 months ago
Cross-Platform Performance Prediction of Parallel Applications Using Partial Execution
Performance prediction across platforms is increasingly important as developers can choose from a wide range of execution platforms. The main challenge remains to perform accurate...
Leo T. Yang, Xiaosong Ma, Frank Mueller
ANSS
2006
IEEE
15 years 8 months ago
Performance Enhancement by Eliminating Redundant Function Execution
Programs often call the same function with the same arguments, yielding the same results. We call this phenomenon, “function reuse”. Previously, we have shown such a behavior ...
Peng Chen, Krishna M. Kavi, Robert Akl
ICPP
2008
IEEE
15 years 8 months ago
Machine Learning Models to Predict Performance of Computer System Design Alternatives
Computer manufacturers spend a huge amount of time, resources, and money in designing new systems and newer configurations, and their ability to reduce costs, charge competitive p...
Berkin Özisikyilmaz, Gokhan Memik, Alok N. Ch...