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119
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HPCA
1999
IEEE
15 years 9 months ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
145
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IPPS
1999
IEEE
15 years 9 months ago
1999
IEEE
In this paper we present the architecture and framework for a benchmark suite that has been developed as part of the DeSiDeRaTa project. The proposed benchmark suite is representat...
131
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IPPS
1998
IEEE
15 years 9 months ago
1998
IEEE
Instruction scheduling methods based on the construction of state diagrams (or automata) have been used for architectures involving deeply pipelined function units. However, the s...
111
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IPPS
1996
IEEE
15 years 9 months ago
1996
IEEE
Virtual memory-mapped communication (VMMC) is a communication model providing direct data transfer between the sender's and receiver's virtual address spaces. This model...
129
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ICS
1989
Tsinghua U.
15 years 9 months ago
1989
Tsinghua U.
Control intensive scalar programs pose a very different challenge to highly pipelined supercomputers than vectorizable numeric applications. Function call/return and branch instru...