Sciweavers

2155 search results - page 356 / 431
» The EM-X Parallel Computer: Architecture and Basic Performan...
Sort
View
COORDINATION
2008
Springer
15 years 6 months ago
Encrypted Shared Data Spaces
Abstract. The deployment of Share Data Spaces in open, possibly hostile, environments arises the need of protecting the confidentiality of the data space content. Existing approach...
Giovanni Russello, Changyu Dong, Naranker Dulay, M...
HPCA
2001
IEEE
16 years 5 months ago
Speculative Data-Driven Multithreading
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
Amir Roth, Gurindar S. Sohi
149
Voted
HPCA
2005
IEEE
16 years 5 months ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner
NETGAMES
2006
ACM
15 years 10 months ago
On correctness of scalable multi-server state replication in online games
Massively Multiplayer Online Games (MMOG) require novel, scalable network architectures for a high amount of participating players in huge game worlds. Consequently, new and compl...
Jens Müller 0004, Andreas Gössling, Serg...
ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 10 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...