2155 search results - page 393 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
HPCA
2007
IEEE
16 years 2 months ago
2007
IEEE
Utilizing the nonuniform latencies of SDRAM devices, access reordering mechanisms alter the sequence of main memory access streams to reduce the observed access latency. Using a r...
104
click to vote
HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
HPCA
2005
IEEE
16 years 2 months ago
2005
IEEE
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
127
click to vote
HPCA
2005
IEEE
16 years 2 months ago
2005
IEEE
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
HPCA
2004
IEEE
16 years 2 months ago
2004
IEEE
Low disk throughput is one of the main impediments to improving the performance of data-intensive servers. In this paper, we propose two management techniques for the disk control...