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HPCA
2005
IEEE
16 years 2 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
HPCA
2001
IEEE
16 years 2 months ago
Self-Tuned Congestion Control for Multiprocessor Networks
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation. Consequently, designers must keep a network below its saturation point...
Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S....
105
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DCOSS
2005
Springer
15 years 7 months ago
Coordinated Static and Mobile Sensing for Environmental Monitoring
Distributed embedded sensor networks are now being successfully deployed in environmental monitoring of natural phenomena as well as for applications in commerce and physical secur...
Richard Pon, Maxim A. Batalin, Victor Chen, Aman K...
EUROPAR
2009
Springer
15 years 6 months ago
SSD-HDD-Hybrid Virtual Disk in Consolidated Environments
Abstract. With the prevalence of multi-core processors and cloud computing, the server consolidation using virtualization has increasingly expanded its territory, and the degree of...
Heeseung Jo, Youngjin Kwon, Hwanju Kim, Euiseong S...
136
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IEEEPACT
2006
IEEE
15 years 7 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal