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MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
15 years 10 months ago
Tradeoffs in designing accelerator architectures for visual computing
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
Aqeel Mahesri, Daniel R. Johnson, Neal C. Crago, S...
ISCA
2003
IEEE
88views Hardware» more  ISCA 2003»
15 years 9 months ago
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-d...
Rajeev Balasubramonian, Sandhya Dwarkadas, David H...
HPDC
2000
IEEE
15 years 8 months ago
RAID-x: A New Distributed Disk Array for I/O-Centric Cluster Computing
A new RAID-x (redundant array of inexpensive disks at level x) architecture is presented for distributed I/O processing on a serverless cluster of computers. The RAID-x architectu...
Kai Hwang, Hai Jin, Roy S. C. Ho
156
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ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
15 years 10 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
ISCA
2007
IEEE
152views Hardware» more  ISCA 2007»
15 years 10 months ago
Carbon: architectural support for fine-grained parallelism on chip multiprocessors
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
Sanjeev Kumar, Christopher J. Hughes, Anthony D. N...