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TVLSI
2008
149views more  TVLSI 2008»
15 years 4 months ago
Architectural Modifications to Enhance the Floating-Point Performance of FPGAs
With the density of FPGAs steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpo...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
AIPR
2008
IEEE
15 years 6 months ago
Low-cost, high-speed computer vision using NVIDIA's CUDA architecture
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
Seung In Park, Sean P. Ponce, Jing Huang, Yong Cao...
ICS
2009
Tsinghua U.
15 years 11 months ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron
TIP
2008
175views more  TIP 2008»
15 years 4 months ago
Algorithmic and Architectural Optimizations for Computationally Efficient Particle Filtering
Abstract--In this paper, we analyze the computational challenges in implementing particle filtering, especially to video sequences. Particle filtering is a technique used for filte...
Aswin C. Sankaranarayanan, Ankur Srivastava, Rama ...
ISVLSI
2002
IEEE
104views VLSI» more  ISVLSI 2002»
15 years 9 months ago
Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation
Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montg...
Adnan Abdul-Aziz Gutub, Alexandre F. Tenca, &Ccedi...