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HPCN
1995
Springer
15 years 8 months ago
A hierarchical approach to workload characterization for parallel systems
Performance evaluation studies are to be an integral part of the design and tuning of parallel applications. We propose a hierarchical approach to the systematic characterization o...
Maria Calzarossa, Alessandro P. Merlo, Daniele Tes...
126
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IPPS
1998
IEEE
15 years 8 months ago
Evaluation of a Low-Power Reconfigurable DSP Architecture
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marl...
SPDP
1993
IEEE
15 years 8 months ago
Architectural Support for Block Transfers in a Shared-Memory Multiprocessor
This paper examines how the performance of a shared-memory multiprocessor can be improved by including hardware support for block transfers. A system similar to the Hector multipr...
Steven J. E. Wilton, Zvonko G. Vranesic
IPPS
1998
IEEE
15 years 8 months ago
Hyper Butterfly Network: A Scalable Optimally Fault Tolerant Architecture
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...
Wei Shi, Pradip K. Srimani
EUROPAR
2000
Springer
15 years 8 months ago
Cache Remapping to Improve the Performance of Tiled Algorithms
With the increasing processing power, the latency of the memory hierarchy becomes the stumbling block of many modern computer architectures. In order to speed-up the calculations, ...
Kristof Beyls, Erik H. D'Hollander