2155 search results - page 99 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
123
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EUROPAR
2009
Springer
15 years 11 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
121
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EUROPAR
1999
Springer
15 years 9 months ago
1999
Springer
Abstract. The High Performance Fortran (HPF) benchmark suite HPFBench was designed for evaluating the HPF language and compilers on scalable architectures. The functionality of the...
128
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SBACPAD
2003
IEEE
15 years 10 months ago
2003
IEEE
— A radiative transfer solver that implements the LTSn method was optimized and parallelized using the MPI message passing communication library. Timing and profiling informatio...
134
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IEEEPACT
2000
IEEE
15 years 9 months ago
2000
IEEE
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
149
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ISPAN
2000
IEEE
15 years 9 months ago
2000
IEEE
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...