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» The Effect of Buffering on the Performance of R-Trees
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CASES
2007
ACM
15 years 1 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
SC
2000
ACM
15 years 1 months ago
The Failure of TCP in High-Performance Computational Grids
Distributed computational grids depend on TCP to ensure reliable end-to-end communication between nodes across the wide-area network (WAN). Unfortunately, TCP performance can be a...
Wu-chun Feng, Peerapol Tinnakornsrisuphap
ISCA
1995
IEEE
133views Hardware» more  ISCA 1995»
15 years 1 months ago
Performance Evaluation of the PowerPC 620 Microarchitecture
The PowerPC 620TM microprocessor1 is the most recent and performance leading member of the PowerPCTM family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch predi...
Trung A. Diep, Christopher Nelson, John Paul Shen
HOTI
2005
IEEE
15 years 3 months ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner
ISCA
1989
IEEE
109views Hardware» more  ISCA 1989»
15 years 1 months ago
Improving Performance of Small On-Chip Instruction Caches
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
Matthew K. Farrens, Andrew R. Pleszkun