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» The Effect of Buffering on the Performance of R-Trees
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HPCA
2006
IEEE
15 years 9 months ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang
SIGCOMM
1994
ACM
15 years 1 months ago
Dynamics of TCP Traffic Over ATM Networks
We investigate the performance of TCP connections over ATM networks without ATM-level congestion control, and compare it to the performance of TCP over packet-based networks. For ...
Allyn Romanow, Sally Floyd
ISCA
1995
IEEE
109views Hardware» more  ISCA 1995»
15 years 1 months ago
Next Cache Line and Set Prediction
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald
88
Voted
TJS
2002
121views more  TJS 2002»
14 years 9 months ago
Precise Data Locality Optimization of Nested Loops
A significant source for enhancing application performance and for reducing power consumption in embedded processor applications is to improve the usage of the memory hierarchy. In...
Vincent Loechner, Benoît Meister, Philippe C...
INFOCOM
2010
IEEE
14 years 8 months ago
Multicast Scheduling with Cooperation and Network Coding in Cognitive Radio Networks
—Cognitive Radio Networks (CRNs) have recently emerged as a promising technology to improve spectrum utilization by allowing secondary users to dynamically access idle primary ch...
Jin Jin, Hong Xu, Baochun Li