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» The Effect of Context Switches on Cache Performance
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125
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MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
15 years 8 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
95
Voted
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
15 years 8 months ago
Adaptive prefetching for shared cache based chip multiprocessors
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
Mahmut T. Kandemir, Yuanrui Zhang, Ozcan Ozturk
112
Voted
ICS
2001
Tsinghua U.
15 years 6 months ago
Integrating superscalar processor components to implement register caching
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
Matt Postiff, David Greene, Steven E. Raasch, Trev...
MTA
2007
79views more  MTA 2007»
15 years 1 months ago
Periodic broadcast with dynamic server selection
Abstract—Service replication is an effective way to address resource requirements and resource availability problem. Dynamic service selection enables clients to choose a server ...
Ewa Kusmierek, Yingping Lu, David Hung-Chang Du
LCPC
2004
Springer
15 years 7 months ago
Empirical Performance-Model Driven Data Layout Optimization
Abstract. Empirical optimizers like ATLAS have been very effective in optimizing computational kernels in libraries. The best choice of parameters such as tile size and degree of l...
Qingda Lu, Xiaoyang Gao, Sriram Krishnamoorthy, Ge...