69 search results - page 3 / 14 » The Effect of Context Switches on Cache Performance |
DSD
2008
IEEE
15 years 1 days ago
2008
IEEE
Caching mechanism has achieved great success in general purpose processor; however, its deployment in Network Processor (NP) raises questions over its effectiveness under the new ...
80
Voted
IEEEPACT
1999
IEEE
15 years 2 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
77
Voted
MAM
2002
14 years 10 months ago
2002
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors. Though many dynamic branch predictors have been proposed to obtain high...
74
Voted
ISCA
1994
IEEE
15 years 2 months ago
1994
IEEE
This paper presents an examination of different cache and processor configurations assuming transistor densities will continue to increase as they have in the past. While in the s...
119
Voted
SIGMETRICS
1993
ACM
15 years 2 months ago
1993
ACM
Recently there has been a surge of interest in developing performance debugging tools to help programmers tune their applications for better memory performance [2, 4, 10]. These t...