69 search results - page 4 / 14 » The Effect of Context Switches on Cache Performance |
89
Voted
ISCA
1994
IEEE
15 years 2 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
94
Voted
SPAA
1993
ACM
15 years 2 months ago
1993
ACM
In this paper we introduce the ConSet communication model for distributed memory parallel computers. The communication needs of an application program can be satisfied by some ar...
135
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VLDB
2007
ACM
15 years 10 months ago
2007
ACM
Main memory cache performance continues to play an important role in determining the overall performance of object-oriented, object-relational and XML databases. An effective metho...
103
Voted
MOBIDE
2005
ACM
15 years 3 months ago
2005
ACM
In the context of mobile data access, data caching is fundamental for both performance and functionality. For this reason there have been many studies into developing energy-effi...
100
Voted
IPPS
2002
IEEE
15 years 3 months ago
2002
IEEE
In this paper, we present an in-depth analysis of the memory system performance of the DSS commercial workloads on two state-of-the-art multiprocessors: the SGI Origin 2000 and th...