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» The Effect of Context Switches on Cache Performance
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137
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CF
2005
ACM
15 years 3 months ago
Controlling leakage power with the replacement policy in slumberous caches
As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is diss...
Nasir Mohyuddin, Rashed Bhatti, Michel Dubois
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 2 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
USENIX
1990
15 years 3 months ago
Efficient User-Level File Cache Management on the Sun Vnode Interface
In developing a distributed file system, there are several good reasons for implementing the client file cache manager as a user-level process. These include ease of implementatio...
David C. Steere, James J. Kistler, Mahadev Satyana...
CF
2007
ACM
15 years 5 months ago
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
Juan M. Cebrian, Juan L. Aragón, José...
91
Voted
ISSS
2002
IEEE
130views Hardware» more  ISSS 2002»
15 years 6 months ago
System-Level Modeling of a Network Switch SoC
We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a desig...
Andrew S. Cassidy, Christopher P. Andrews, Donald ...