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MICRO
2000
IEEE
72views Hardware» more  MICRO 2000»
14 years 9 months ago
PipeRench implementation of the instruction path coprocessor
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
INFOCOM
2007
IEEE
15 years 3 months ago
The Cache Inference Problem and its Application to Content and Request Routing
— In many networked applications, independent caching agents cooperate by servicing each other’s miss streams, without revealing the operational details of the caching mechanis...
Nikolaos Laoutaris, Georgios Zervas, Azer Bestavro...
WMPI
2004
ACM
15 years 2 months ago
A compressed memory hierarchy using an indirect index cache
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
Erik G. Hallnor, Steven K. Reinhardt
LFP
1992
140views more  LFP 1992»
14 years 10 months ago
Global Tagging Optimization by Type Inference
Tag handling accounts for a substantial amount of execution cost in latently typed languages such as Common LISP and Scheme, especially on architectures that provide no special ha...
Fritz Henglein
77
Voted
PLDI
1996
ACM
15 years 1 months ago
Fast, Effective Dynamic Compilation
Dynamic compilation enables optimizations based on the values of invariant data computed at run-time. Using the values of these runtime constants, a dynamic compiler can eliminate...
Joel Auslander, Matthai Philipose, Craig Chambers,...