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IPPS
1999
IEEE
15 years 1 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
15 years 6 months ago
SPM management using Markov chain based data access prediction
— Leveraging the power of scratchpad memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular a...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
15 years 2 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
CN
2006
145views more  CN 2006»
14 years 9 months ago
Understanding optimal data gathering in the energy and latency domains of a wireless sensor network
The problem of optimal data gathering in wireless sensor networks (WSNs) is addressed by means of optimization techniques. The goal of this work is to lay the foundations to devel...
Ugo Monaco, Francesca Cuomo, Tommaso Melodia, Fabi...
TCAD
2008
172views more  TCAD 2008»
14 years 9 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...