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DAC
2000
ACM
15 years 5 months ago
An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component m
Abstract: This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circ...
Carlo Guardiani, Sharad Saxena, Patrick McNamara, ...
104
Voted
CVPR
2010
IEEE
15 years 5 months ago
Learning Weights for Codebook in Image Classification
This paper presents a codebook learning approach for image classification and retrieval. It corresponds to learning a weighted similarity metric to satisfy that the weighted simil...
Hongping Cai, Krystian Mikolajczyk, Fei Yan
ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
15 years 5 months ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram
95
Voted
DATE
1999
IEEE
102views Hardware» more  DATE 1999»
15 years 5 months ago
Minimal Length Diagnostic Tests for Analog Circuits using Test History
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...
Alfred V. Gomes, Abhijit Chatterjee
83
Voted
ISPD
1999
ACM
94views Hardware» more  ISPD 1999»
15 years 5 months ago
Gate sizing with controlled displacement
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram