392 search results - page 47 / 79 » The Entropy of FPGA Reconfiguration |
116
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FPL
2004
Springer
15 years 5 months ago
2004
Springer
A concept for solving the communication problem among modules dynamically placed on a reconfigurable device is presented. Based on a dynamic network-on-chip (DyNoC) communication i...
118
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CHES
2006
Springer
15 years 5 months ago
2006
Springer
Abstract. Many Field-Programmable Gate Array (FPGA) based systems utilize third-party intellectual property (IP) in their development. When they are deployed in non-networked envir...
125
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Publication
_2011.jpg "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision")
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...
FPL
2007
Springer
15 years 7 months ago
2007
Springer
The reconfigurable mesh is a model for massively parallel computing for which many algorithms with very low complexity have been developed. These algorithms execute cycles of bus...
ISVLSI
2003
IEEE
15 years 6 months ago
2003
IEEE
This paper presents the design and implementation of the new Active Memory Manager Unit (AMMU) designed to be embedded into System-on-Chip CPUs. The unit is implemented using VHDL...