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» The Entropy of FPGA Reconfiguration
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FPL
2004
Springer
112views Hardware» more  FPL 2004»
15 years 6 months ago
Automating the Layout of Reconfigurable Subsystems via Template Reduction
When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion o...
Shawn Phillips, Akshay Sharma, Scott Hauck
FPL
2008
Springer
125views Hardware» more  FPL 2008»
15 years 3 months ago
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconf...
Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dud...
ERSA
2009
129views Hardware» more  ERSA 2009»
14 years 11 months ago
Data path Configuration Time Reduction for Run-time Reconfigurable Systems
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabe...
RECONFIG
2009
IEEE
172views VLSI» more  RECONFIG 2009»
15 years 8 months ago
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Abstract—The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customar...
Shivam Bhasin, Jean-Luc Danger, Florent Flament, T...
DELTA
2010
IEEE
15 years 6 months ago
Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor
Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of...
Hans G. Kerkhoff, Xiao Zhang