392 search results - page 70 / 79 » The Entropy of FPGA Reconfiguration |
115
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INTEGRATION
2008
14 years 12 months ago
2008
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
114
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TVLSI
2010
14 years 8 months ago
2010
In many applications, a reduction of the amount of the original data or a representation of the original data by a small set of variables is often required. Among many techniques, ...
102
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RECONFIG
2009
IEEE
15 years 8 months ago
2009
IEEE
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
121
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ASAP
2008
IEEE
15 years 7 months ago
2008
IEEE
This article discusses the design of an application specific MPSoC architecture dedicated to Multiple Target Tracking (MTT). This application has its utility in driver assistant s...
139
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ICRA
2006
IEEE
15 years 7 months ago
2006
IEEE
– To make a mobile robot with real-time vision system adapt to the highly dynamic environments and emergencies under the real-time constraints, a significant account of processin...