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» The Entropy of FPGA Reconfiguration
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ICS
2009
Tsinghua U.
15 years 8 months ago
High-performance CUDA kernel execution on FPGAs
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Alexandros Papakonstantinou, Karthik Gururaj, John...
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 7 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
DAC
2006
ACM
16 years 2 months ago
Leakage power reduction of embedded memories on FPGAs through location assignment
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
Yan Meng, Timothy Sherwood, Ryan Kastner
RECONFIG
2009
IEEE
182views VLSI» more  RECONFIG 2009»
15 years 8 months ago
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...
Siddhartha Datta, Ron Sass
AHS
2006
IEEE
138views Hardware» more  AHS 2006»
15 years 7 months ago
Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures
Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has sh...
Emanuele Stomeo, Tatiana Kalganova, Cyrille Lamber...