Sciweavers

988 search results - page 22 / 198
» The Frontiers of Data Programmability
Sort
View
DAC
1997
ACM
15 years 1 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
Marleen Adé, Rudy Lauwereins, J. A. Peperst...
FPGA
1997
ACM
124views FPGA» more  FPGA 1997»
15 years 1 months ago
YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing
This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a network contr...
Akihiro Tsutsui, Toshiaki Miyazaki
SCN
2008
Springer
136views Communications» more  SCN 2008»
14 years 9 months ago
An efficient data structure for network anomaly detection
Abstract-- Despite the rapid advance in networking technologies, detection of network anomalies at high-speed switches/routers is still far from maturity. To push the frontier, two...
Jieyan Fan, Dapeng Wu, Kejie Lu, Antonio Nucci
IPPS
2000
IEEE
15 years 1 months ago
PDRS: A Performance Data Representation System
We present the design and development of a Performance Data Representation System (PDRS) for scalable parallel computing. PDRS provides decision support that helps users find the r...
Xian-He Sun, Xingfu Wu
PDP
2008
IEEE
15 years 3 months ago
Out-of-Core Wavefront Computations with Reduced Synchronization
Matrix computation algorithms often exhibit dependencies between neighboring elements inside loop nests such that the frontier between computed elements and those to be computed w...
Pierre-Nicolas Clauss, Jens Gustedt, Fréd&e...