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CCGRID
2003
IEEE
15 years 6 months ago
Preliminary Evaluation of Dynamic Load Balancing Using Loop Re-partitioning on Omni/SCASH
Increasingly large-scale clusters of PC/WS continue to become majority platform in HPC field. Such a commodity cluster environment, there may be incremental upgrade due to severa...
Yoshiaki Sakae, Mitsuhisa Sato, Satoshi Matsuoka, ...
IPPS
2003
IEEE
15 years 6 months ago
ECO: An Empirical-Based Compilation and Optimization System
In this paper, we describe a compilation system that automates much of the process of performance tuning that is currently done manually by application programmers interested in h...
Nastaran Baradaran, Jacqueline Chame, Chun Chen, P...
84
Voted
ITC
2003
IEEE
176views Hardware» more  ITC 2003»
15 years 6 months ago
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
Olivier Caty, Ismet Bayraktaroglu, Amitava Majumda...
105
Voted
PG
2003
IEEE
15 years 6 months ago
High-Quality Point-Based Rendering on Modern GPUs
In the last years point-based rendering has been shown to offer the potential to outperform traditional triangle based rendering both in speed and visual quality when it comes to ...
Mario Botsch, Leif Kobbelt
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 5 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...