Current hardware transactional memory systems seek to simplify parallel programming, but assume that large transactions are rare, so it is acceptable to penalize their performance...
Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael...
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
Kieron Turkington, Turkington A. Constantinides, K...
Functionality for various services of scheduling algorithms is typically provided as extensions to a basic algorithm. Aperiodic task handling, guarantees, etc., are integrated wit...
In this paper, our contributions are two-fold: First, we enhance the Min-Min and Sufferage heuristics under three risk modes driven by security concerns. Second, we propose a new ...
Many of today's Web applications support just simple trial-anderror retrievals: supply one set of parameters, obtain one set of results. For a user who wants to examine a num...