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RTSS
1999
IEEE
15 years 10 months ago
Timing Anomalies in Dynamically Scheduled Microprocessors
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
Thomas Lundqvist, Per Stenström
LCPC
1999
Springer
15 years 10 months ago
Compiling for Speculative Architectures
The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, targeting the generated code to a speculative para...
Seon Wook Kim, Rudolf Eigenmann
LCN
1998
IEEE
15 years 10 months ago
High Performance Integrated Network Communications Architecture (INCA)
Current communication subsystem mechanisms within workstation and PC class computers are limiting network communications throughput to a small percentage of the present network da...
Klaus Schug, Anura P. Jayasumana, Prasanth Gopalak...
RTAS
1998
IEEE
15 years 10 months ago
Bounding Loop Iterations for Timing Analysis
Static timing analyzers need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. ...
Christopher A. Healy, Mikael Sjödin, Viresh R...
FMCAD
1998
Springer
15 years 10 months ago
Symbolic Simulation: An ACL2 Approach
Executable formal speci cation can allow engineers to test (or simulate) the speci ed system on concrete data before the system is implemented. This is beginning to gain acceptance...
J. Strother Moore
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