Sciweavers

617 search results - page 102 / 124
» The General Architecture of Generation in ACORD
Sort
View
CGO
2008
IEEE
15 years 4 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
100
Voted
MOBIQUITOUS
2008
IEEE
15 years 4 months ago
ScreenSpot: multidimensional resource discovery for distributed applications in smart spaces
The big challenge related to the contemporary research on ubiquitous and pervasive computing is that of seamless integration. For the next generation of ubiquitous and distributed...
Marko Jurmu, Sebastian Boring, Jukka Riekki
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
EMSOFT
2007
Springer
15 years 3 months ago
WCET estimation for executables in the presence of data caches
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
Rathijit Sen, Y. N. Srikant
LCTRTS
2007
Springer
15 years 3 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...