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DAC
2006
ACM
15 years 10 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
GECCO
2007
Springer
158views Optimization» more  GECCO 2007»
15 years 3 months ago
A novel generative encoding for exploiting neural network sensor and output geometry
A significant problem for evolving artificial neural networks is that the physical arrangement of sensors and effectors is invisible to the evolutionary algorithm. For example,...
David B. D'Ambrosio, Kenneth O. Stanley
CODES
2005
IEEE
15 years 3 months ago
Dynamic phase analysis for cycle-close trace generation
For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system em...
Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh...
LCN
2005
IEEE
15 years 3 months ago
Network Management Challenges for Next Generation Networks
Generally, current network management technologies follow two approaches: ITU-T’s recommendations for Telecommunication Management Network (TMN) and IETF’s Simple Network Mana...
Mo Li, Kumbesan Sandrasegaran
OOPSLA
2010
Springer
14 years 7 months ago
Towards a tool-based development methodology for sense/compute/control applications
This poster presents a design language and a tool suite covering the development life-cycle of a Sense/Compute/Control (SCC) application. This language makes it possible to define...
Damien Cassou, Julien Bruneau, Julien Mercadal, Qu...