Sciweavers

617 search results - page 94 / 124
» The General Architecture of Generation in ACORD
Sort
View
DAC
2006
ACM
15 years 1 months ago
Steiner network construction for timing critical nets
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open f...
Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
DAC
2005
ACM
14 years 11 months ago
Matlab as a development environment for FPGA design
In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algo...
Tejas M. Bhatt, Dennis McCain
DAC
2005
ACM
14 years 11 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
79
Voted
DAC
2005
ACM
14 years 11 months ago
A watermarking system for IP protection by a post layout incremental router
In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (Data Encryption Standard) and then ...
Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga
87
Voted
DAC
2005
ACM
14 years 11 months ago
Modular domain-specific implementation and exploration framework for embedded software platforms
This paper focuses on designing network processing software for embedded processors. Our design flow CRACC represents an efficient path to implementation based on a modular applic...
Christian Sauer, Matthias Gries, Sören Sonnta...