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» The Generalized Dimensionality Reduction Problem
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DAC
2011
ACM
13 years 9 months ago
Fault-tolerant 3D clock network
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...
COMSNETS
2012
297views more  COMSNETS 2012»
13 years 5 months ago
Optimizing cloud resources for delivering IPTV services through virtualization
—Virtualized cloud-based services can take advantage of statistical multiplexing across applications to yield significant cost savings to the operator. However, achieving simila...
Vaneet Aggarwal, Vijay Gopalakrishnan, Rittwik Jan...
DAC
2003
ACM
15 years 10 months ago
On-chip logic minimization
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
Roman L. Lysecky, Frank Vahid
POPL
2008
ACM
15 years 10 months ago
Foundations for structured programming with GADTs
GADTs are at the cutting edge of functional programming and become more widely used every day. Nevertheless, the semantic foundations underlying GADTs are not well understood. In ...
Patricia Johann, Neil Ghani
SIGMOD
2009
ACM
198views Database» more  SIGMOD 2009»
15 years 9 months ago
Monitoring path nearest neighbor in road networks
This paper addresses the problem of monitoring the k nearest neighbors to a dynamically changing path in road networks. Given a destination where a user is going to, this new quer...
Zaiben Chen, Heng Tao Shen, Xiaofang Zhou, Jeffrey...