1187 search results - page 91 / 238 » The Generalized Dimensionality Reduction Problem |
FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
ISPD
2005
ACM
15 years 3 months ago
2005
ACM
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
COMPGEOM
2009
ACM
15 years 4 months ago
2009
ACM
We present cache-oblivious solutions to two important variants of range searching: range reporting and approximate range counting. Our main contribution is a general approach for ...
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FOCS
2008
IEEE
14 years 11 months ago
2008
IEEE
In the mobile facility location problem, which is a variant of the classical Uncapacitated Facility Location and kMedian problems, each facility and client is assigned to a start ...