47 search results - page 2 / 10 » The Identification of registers in RTL Structures for the Te... |
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
ICCAD
2007
IEEE
13 years 10 months ago
2007
IEEE
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
ICCAD
1995
IEEE
13 years 9 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
HOST
2009
IEEE
13 years 4 months ago
2009
IEEE
Abstract-- We report our experiences in designing and implementing several hardware Trojans within the framework of the Embedded System Challenge competition that was held as part ...
EURODAC
1994
IEEE
13 years 10 months ago
1994
IEEE
The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test reg...