— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
Abstract— Efficient bandwidth allocation strategy with simultaneous fulfillment of QoS requirement of a user in a mobile cellular network is still a critical and an important p...