1516 search results - page 180 / 304 » The Increasing Nvalue Constraint |
111
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ICCAD
2007
IEEE
16 years 29 days ago
2007
IEEE
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. As a result, a paradigm shift from determ...
141
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ICCAD
2004
IEEE
16 years 29 days ago
2004
IEEE
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
111
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ICCAD
2004
IEEE
16 years 29 days ago
2004
IEEE
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
123
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ICCAD
2004
IEEE
16 years 29 days ago
2004
IEEE
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
139
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FPGA
2010
ACM
16 years 28 days ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...