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HPCA
2009
IEEE
16 years 12 days ago
Blueshift: Designing processors for timing speculation from the ground up
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey ...
MOBIHOC
2009
ACM
16 years 12 days ago
Experimental characterization of sectorized antennas in dense 802.11 wireless mesh networks
Sectorized antennas can increase wireless network capacity through greater spatial reuse. Despite their increasing popularity, their real-world performance characteristics in dens...
Anand Prabhu Subramanian, Henrik Lundgren, Theodor...
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 8 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
15 years 8 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
15 years 8 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...