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DATE
2006
IEEE
87views Hardware» more  DATE 2006»
15 years 3 months ago
Thermal resilient bounded-skew clock tree optimization methodology
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
Ashutosh Chakraborty, Prassanna Sithambaram, Karth...
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
15 years 3 months ago
A methodology for mapping multiple use-cases onto networks on chips
A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for future Systems on C...
Srinivasan Murali, Martijn Coenen, Andrei Radulesc...
AIED
2005
Springer
15 years 3 months ago
The Effect of Explaining on Learning: a Case Study with a Data Normalization Tutor
: Several studies have shown that explaining actions increases students’ knowledge. In this paper, we discuss how NORMIT supports self-explanation. NORMIT is a constraint-based t...
Antonija Mitrovic
ASAP
2003
IEEE
108views Hardware» more  ASAP 2003»
15 years 3 months ago
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
Terry Tao Ye, Giovanni De Micheli
ESANN
2003
14 years 11 months ago
Developmental pruning of synapses and category learning
After an initial peak, the number of synapses in mammalian cerebral cortex decreases in the formative period and throughout adult life. However, if synapses are taken to reflect ci...
Roberto Viviani, Manfred Spitzer