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DATE
2002
IEEE
94views Hardware» more  DATE 2002»
15 years 2 months ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
15 years 2 months ago
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders
—As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the co...
Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park
PLDI
2000
ACM
15 years 2 months ago
Optimal instruction scheduling using integer programming
{ This paper presents a new approach to local instruction scheduling based on integer programming that produces optimal instruction schedules in a reasonable time, even for very la...
Kent D. Wilken, Jack Liu, Mark Heffernan
ICCAD
1994
IEEE
144views Hardware» more  ICCAD 1994»
15 years 2 months ago
Power analysis of embedded software: a first step towards software power minimization
Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical com...
Vivek Tiwari, Sharad Malik, Andrew Wolfe
CASES
2007
ACM
15 years 1 months ago
Cache leakage control mechanism for hard real-time systems
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transi...
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia...