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» The Inherent Queuing Delay of Parallel Packet Switches
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PODC
1997
ACM
15 years 2 months ago
Leap Forward Virtual Clock: A New Fair Queuing Scheme with Guaranteed Delays and Throughput Fairness
We describe an ejjicient fair queuing scheme, Leap Forward Virtual Clock, that provides end-to-end delay bounds simdar to WFQ, along with throughput fairness. Our scheme can be im...
Subhash Suri, George Varghese, Girish P. Chandranm...
INFOCOM
2008
IEEE
15 years 4 months ago
Fair Scheduling through Packet Election
—In this paper, we consider the problem of designing scheduling algorithm for input queued switch that is both fair as well as throughput optimal. The significant body of litera...
Srikanth Jagabathula, Vishal Doshi, Devavrat Shah
IPPS
1998
IEEE
15 years 2 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
ICPP
2007
IEEE
15 years 4 months ago
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
As the number of computing and storage nodes keeps increasing, the interconnection network is becoming a key element of many computing and communication systems, where the overall...
Gaspar Mora, Pedro Javier García, Jose Flic...
HOTI
2002
IEEE
15 years 2 months ago
A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
François Abel, Cyriel Minkenberg, Ronald P....