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» The Inherent Queuing Delay of Parallel Packet Switches
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INFOCOM
2002
IEEE
15 years 2 months ago
Scheduling Processing Resources in Programmable Routers
—To provide flexibility in deploying new protocols and services, general-purpose processing engines are being placed in the datapath of routers. Such network processors are typi...
Prashanth Pappu, Tilman Wolf
ICC
1997
IEEE
158views Communications» more  ICC 1997»
15 years 2 months ago
The Priority Token Bank in a Network of Queues
This paper takes a known approach for scheduling and admission control in integrated services networks1 , the Priority Token Bank (PTB), whose mechanism and performance have been ...
Mark A. Lynn, Jon M. Peha
ANCS
2006
ACM
15 years 1 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
INFOCOM
2006
IEEE
15 years 4 months ago
Analyzing the Receiver Window Modification Scheme of TCP Queues
– Explicit Congestion Notification (ECN) and Active Queue Management (AQM) Schemes such as Random Early Detection (RED), Adaptive Random Early Detection (ARED) and BLUE queues ha...
Visvasuresh Victor Govindaswamy, Gergely V. Z&aacu...
INFOCOM
2002
IEEE
15 years 2 months ago
Towards Simple, High-performance Schedulers for High-aggregate Bandwidth Switches
— High-aggregate bandwidth switches are those whose port count multiplied by the operating line rate is very high; for example, a 30 port switch operating at 40 Gbps or a 1000 po...
Paolo Giaccone, Balaji Prabhakar, Devavrat Shah